A known approach for fabricating a 14 nm lower-power n-type field-effect transistor (NFET) includes forming the S/D regions with a single epi-silicon phosphorous (epi-SiP) layer that is in-situ doped with a high concentration of phosphorous (P), as depicted in FIG. 1. Adverting to FIG. 1 (an axiomatic view), an STI region 101 is formed between fin 103 and an adjacent fin (not shown for illustrative convenience). A gate dielectric layer 105 and a gate structure 107 are then formed over the fin 103 between a high P concentration epi-SiP S/D region 109 and a second S/D region (not shown for illustrative convenience), with spacers 111 and 113 on each side of the gate structure 107. The high P concentration in the epi-SiP S/D region 109 is good for boosting the direct current (DC) performance of the device. However, such concentrations also create an abrupt P dopant concentration transition from the channel to the extension region and induce strong band to band generation, both of which are a root cause of low breakdown voltage (BV) and high substrate current (Isub) in these kind of devices.
The traditional approach for solving these problems is tuning the implant conditions to reduce the steepness of the doping profiles. However, tuning the halo/extension/pre-ion implant/S/D implant conditions without largely degrading the DC performance of the device results in only a limited improvement of BV and Isub of the device.
A need therefore exists for methodology enabling formation of a graded P dopant concentration distribution from the channel to the extension region of an NFET, and the resulting device.